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As the chip carrier is the interface for the semiconductor device, printed wiring boards (PWBs) serve as the interface for the chip carrier packages.
They are usually made from organic laminated materials which consist of a particular resin (epoxy, polymide, phenolic) embedded with some type of reinforcement (glass, paper, combinations thereof) and have
copper foil attached to the outer surfaces. They are referred to as copper clad industrial laminates.
The structure of the PWB, which comprises layers of power and signal planes as well as wiring density, is determined by the type, number and placement of those packages. Historically, there has been
a trend toward decreasing line widths and spaces while layer counts have gradually increased. This migration can be tied to increasing chip I/O densities. In addition to circuit density, PWB designers must
provide for increased and improved thermal and electrical management, such as controlled impedance wiring layers. Complications can occur if there are space or weight constraints imposed by the end use
application, such as in laptops or hand-held devices. In these cases, layer counts can only increase if each plane in the PWB is reduced in thickness, which then creates handling concerns during manufacture.
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