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Ceramic chip carriers are fabricated with either alumina (Al2O3) dielectric and molybdenum conductors or Cordierite
glass dielectric with copper conductors. They can be used in high performance applications with I/O exceeding 1,600 pins and chips up to 30mm in size. The chips are flipped and joined to the carrier with
small solder balls in a process called Controlled Collapsible Chip Connection (C4).
The C4 flip-chip connection provides high I/O density, uniform chip power distribution, improved cooling capability, and high reliability. This technology, coupled with IBM's advanced packaging, has
been used to build some of the highest density electronic components in the industry. C4 technology has increased packaging density, data bandwidths, and operating frequencies while reducing system-level
noise.
Originally introduced by IBM in the early 1960s, the C4 of today is a process that uses 97/3% PbSn solder balls with diameters ranging from 100 to 125 microns as a chip-to-carrier interconnect. An array
of these balls or bumps are arranged around the surface of a chip, either in an area array or peripheral configuration. The chip is placed face down on a carrier. When heat is applied, the solder reflows
to the pads joining the chip to the carrier.
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