It's 2:00 a.m. and you can't sleep. Something is bothering you. Your die is cast. Finally, after months of painful planning and development, your chips
are coming off the semiconductor assembly line. That's the good news. The bad news is that you just talked to your packaging application engineer at the XYZ Assembly Factory. Remember that low cost, off-the-shelf,
commodity package that you recently chose? Well, guess what? Your chip throws off a little more heat than that package can handle. About .5 to 1 watt more! Looks like you need a cavity-down packaging solution
instead.
Unfortunately, this scenario is all too common. The dizzying pace of silicon integration has pushed the packaging envelope with regard to heat dissipation, electrical performance and mechanical integrity.
Heat is generated as a result of electrical energy being converted to thermal energy during circuit activities. It doesn't take a rocket scientist to determine that the circuits in today's advanced ASICs
and microprocessors generate lots of heat. The junction temperature of a chip directly affects circuit performance and the reliability of the package. It's a problem that everyone in the interconnect business
is scrambling to solve.
